Dual-FPGA hardware platform assembled
The dual-FPGA hardware platform has been assembled for laboratory bring-up.
Engineering Program
FPGA & Video
High-Bandwidth Dual-FPGA Display Platform
A dual-FPGA video processing platform under development for high-resolution, high-refresh display applications.
Reference Architecture
- Application
- High-resolution display processing
- Engineering Scope
- Dual-FPGA platform, link control, panel bring-up
- Interface Domain
- Multi-link eDP
- Project Status
- Engineering Program
Project Overview
The program focuses on multi-link video transport, FPGA partitioning, deterministic synchronization and panel bring-up, with a path for subsequent real-time display processing.
Engineering Challenge
Receive-to-transmit timing, parallel-path synchronization and panel compatibility have to be closed on the same high-bandwidth link.
Engineering Scope
- System architecture and interface definition
- FPGA pipeline design and integration
- Link training and signal-margin validation
- Panel, backlight or interface validation
- Prototype bring-up and laboratory debugging
Engineering Approach
Hardware partitioning and link bring-up come first. Application-specific processing is prepared on the same architecture after receive and transmit paths are stable.
Current Engineering Focus
- Link stability across target modes
- Synchronization between parallel processing paths
- Timing integrity
- Panel compatibility
- Preparation for application-specific processing
Engineering Targets
- 5K resolution
- High-refresh operation
- Target refresh rate
- Target lane configuration
- Future local dimming integration
Completed Engineering Steps
Receive and transmit paths brought up
Receive and transmit video paths have been brought up on the assembled platform.
Multi-link architecture integrated
The multi-link receive and transmit architecture has been integrated on the dual-FPGA partition.
Panel bring-up completed for selected operating modes
Panel bring-up has been completed for selected operating modes on the current hardware.
Reference Architecture
Deliverables
- Architecture document
- FPGA implementation under the active program
- Bring-up notes against agreed tests
Related work
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