Dual-FPGA hardware platform assembled
The dual-FPGA hardware platform has been assembled for laboratory bring-up.
FPGA & Video
High-Bandwidth Dual-FPGA Display Platform
A dual-FPGA video processing platform under development for high-resolution, high-refresh display applications.
Reference Architecture
- Application
- High-resolution display processing
- Work covered
- Dual-FPGA platform, link control, panel bring-up
- Interface Domain
- Multi-link eDP
Project Overview
A dual-FPGA display platform: multi-link eDP receive and transmit, partitioned by bandwidth, latency, memory and panel timing.
Engineering Challenge
Receive-to-transmit timing, parallel-path synchronization and panel compatibility have to close on that same link.
Engineering Scope
- System architecture and interface definition
- FPGA pipeline design and integration
- Link training and signal-margin validation
- Panel, backlight or interface validation
- Prototype bring-up and laboratory debugging
Engineering Approach
Yunxin partitions the two FPGAs and brings up the receive and transmit paths. Application processing is prepared on that architecture after those paths are stable.
Engineering Work
- Link stability across target modes
- Synchronization between parallel processing paths
- Timing integrity
- Panel compatibility
- Preparation for application-specific processing
Engineering Targets
- 5K resolution
- High-refresh operation
- Future local dimming integration
Engineering Work
Receive and transmit paths brought up
Receive and transmit video paths have been brought up on the assembled platform.
Multi-link architecture integrated
The multi-link receive and transmit architecture has been integrated on the dual-FPGA partition.
Panel bring-up completed for selected operating modes
Panel bring-up has been completed for selected operating modes on the current hardware.
Deliverables
- Architecture document
- FPGA implementation under the active program
- Bring-up notes against agreed tests