FPGA processing architecture
Processing architecture is defined for geometric correction on the FPGA video path.
Engineering Program
FPGA & Video
HUD Warping & Binocular Fusion
An FPGA-based processing program for geometric correction and binocular image composition in specialized display systems.
Reference Architecture
- Application
- Specialized display geometry and fusion
- Engineering Scope
- FPGA processing, hardware definition, interface integration
- Key Interfaces
- Video I/O, DDR / frame buffer
- Project Status
- Engineering Program
Project Overview
This engineering program focuses on FPGA processing architecture, warp-map integration and binocular image composition for project-specific optical systems.
Engineering Challenge
Geometry correction and binocular composition have to stay inside the latency budget while consuming calibration maps in a form the FPGA pipeline can use.
Engineering Approach
The engineering scope covered processing architecture and map-format constraints before RTL expands, then interface integration and composition on the target hardware class.
Current Engineering Focus
- Calibration-map integration on the FPGA path
- Left/right-eye composition timing
- Frame-buffer and latency budget
- Video interface bring-up
Engineering Scope
Warp-map data path
The data path is planned so calibration maps can be consumed by the FPGA pipeline.
Left/right-eye composition
Binocular composition is included in the processing scope for the agreed optical setup.
External calibration-map integration
External warp maps are integrated according to the contracted map format.
Memory and video-interface planning
DDR buffering and video I/O are planned against the latency and interface constraints of the optical system.
Reference Architecture
Program Deliverables
- Architecture definition
- Hardware design scope
- FPGA source-code scope as defined by contract
- Integration and validation plan
Related work
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