FPGA processing architecture
Processing architecture is defined for geometric correction on the FPGA video path.
FPGA & Video
HUD Warping & Binocular Fusion
An FPGA-based processing program for geometric correction and binocular image composition in specialized display systems.
Reference Architecture
- Application
- Specialized display geometry and fusion
- Work covered
- FPGA processing, hardware definition, interface integration
- Key Interfaces
- Video I/O, DDR / frame buffer
Project Overview
FPGA processing for geometric correction and binocular composition on a project-specific optical system, with DDR buffering on the video path.
Engineering Challenge
Warp maps and left/right composition have to stay inside the latency budget of that optical setup.
Engineering Approach
Yunxin defines the processing architecture and the map format, then integrates video I/O, DDR buffering and left/right composition on the target hardware class.
Engineering Work
- Calibration-map integration on the FPGA path
- Left/right-eye composition timing
- Frame-buffer and latency budget
- Video interface bring-up
Engineering Scope
Warp-map data path
The data path is planned so calibration maps can be consumed by the FPGA pipeline.
Left/right-eye composition
Binocular composition is included in the processing scope for the agreed optical setup.
External calibration-map integration
External warp maps enter the FPGA pipeline in the format defined for that optical setup.
Memory and video-interface planning
DDR buffering and video I/O are planned against the latency and interface constraints of the optical system.
Program Deliverables
- Architecture definition
- Hardware design scope
- FPGA source for the defined program
- Integration and validation plan